On September 7, John Savage (with Andre' DeHon of UPenn) received a collaborative research grant from the National Science Foundation to study coded computation and storage at the nanoscale.

A key challenge before the semiconductor industry is coping with high error rates resulting from the decreasing size of chip features. Transient faults, along with permanent defects and stochastic assembly, make it difficult to implement traditional architectures. Research has been done on routing around defects and coping with large amounts of device variation. Little is known, however, about how to cope efficiently with high-rates of transient errors during computation. This research ...